This invention relates to a current sense circuit.
A semiconductor integrated circuit tester is used for testing semiconductor integrated circuit devices having numerous I/O pins. The tester has numerous tester pins for connection to the I/O pins respectively of a device under test (DUT) and a pin electronics circuit is associated with each tester pin. It is known for the pin electronics circuit to be integrated in a CMOS integrated circuit die. Depending on its mode of operation, each pin electronics circuit can supply a stimulus signal to the corresponding DUT pin or receive a response signal from the DUT pin.
The pin electronics circuit may include a force amplifier for forcing a specified voltage on a pin of the DUT. The current flowing into the DUT pin is converted to a voltage by a current sense resistor and the voltage drop across the current sense resistor is amplified by a differential amplifier, which is also included in the pin electronics circuit and provides an output voltage referenced to ground and proportional to the current through the current sense resistor. The output voltage of the differential amplifier is measured or is compared to fixed high and low limits. This type of test is commonly known as a parametric measurement unit (PMU) test and typically verifies that the connection between the pin and the tester is correct and that the leakage current at the pin is less than a specified maximum.
The range of current values that can be measured depends on the resistance value of the current sense resistor and the input range of the differential amplifier. If a wide dynamic range of current is to be measured without loss of accuracy, the resistance of the current sense resistor must be selectively variable. This may be accomplished by using a network of resistors, of different values, and a switch for selecting one of the resistors depending on the current range to be measured. Hitherto, the network of resistors has been implemented by discrete physical resistors which are external of the CMOS integrated circuit in which the pin electronics are implemented and are individually selected by relays or solid state switches. The discrete physical resistors and the associated relays require considerable space at each pin.